Search - fpga pc

[Com Port] FPGA

Description: 本文介绍了一种新的使用串行通信进行DSP远程在线编程方法。对设计中的主要技术：DSP与PC机的串口通信、Flash编程以及DSP自引导等进行了详细介绍。结合TI公司的TMS320VC33处理器，阐述了具体的实现方法
Platform: | Size: 54543 | Author: roger | Hits:

[Other resource] 基于FPGA的直接数字合成器设计

Description: 1、利用FLEX10的片内RAM资源，根据DDS原理，设计产生正弦信号的各功能模块和顶层原理图； 2、利用实验板上的TLC7259转换器，将1中得到的正弦信号，通过D/A转换，通过ME5534滤波后在示波器上观察； 3、输出波形要求：在输入时钟频率为16KHz时，输出正弦波分辨率达到1Hz；在输入时钟频率为4MHz时，输出正弦波分辨率达到256Hz； 4、通过RS232C通信，实现FPGA和PC机之间串行通信，从而实现用PC机改变频率控制字，实现对输出正弦波频率的控制。-a use FLEX10-chip RAM resources, in accordance with DDS principle, design sinusoidal signal generated by the top-level functional modules and schematics; 2, the experimental board TLC7259 converters, will be a sinusoidal signal, the D / A conversion, after filtering through the ME5534 oscilloscope observation; 3, the output waveform requirements : the input clock frequency of 16KHz, sine wave output resolution of 1Hz; the input clock frequency of 4MHz, the sine wave output resolution of 256Hz; 4, RS232C communications, FPGA and PC serial communications between in order to achieve PC-frequency control characters, the realization of sine wave output frequency control.
Platform: | Size: 22183 | Author: 竺玲玲 | Hits:

[Communication] fpga与PC机的串口通信

Description: 基于VerilogHDL 的FPGA与PC的串口通信代码，已经测试过，绝对可以用
Platform: | Size: 444975 | Author: z343468478 | Hits:

[VHDL-FPGA-Verilog] uart from opencores

Description: 用VHDL实现串口可以实现与pc机的通信收发中断都可以效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
Platform: | Size: 9216 | Author: 熊明 | Hits:

[Com Port] DSP-com

Description: 介绍DSP与上微机的串口通信和功能设置，及通信调试-introduced DSP and PC on the serial communications and functionality, and communication Debugging
Platform: | Size: 80896 | Author: mwh | Hits:

[VHDL-FPGA-Verilog] Exp6-VGA

Description: 通过UART从PC主机读取图片数据，并完成图片在VGA显示器上的显示-through UART from the host PC to read image data, and complete picture of the VGA display on the show
Platform: | Size: 681984 | Author: 萧飒 | Hits:

[VHDL-FPGA-Verilog] uart0vhdl

Description: vhdl实现fpga和PC机的简单通信(发送),-vhdl achieve fpga and PC simple communication (transmission),
Platform: | Size: 1024 | Author: 刘音 | Hits:

[Other Embeded program] epp_sram

Description: verilog语言编写的FPGA代码。功能为pc机通过epp不断写数到sram中，然后pc发送中断信号打断写过程读取sram中的数据。rar包中包含epp协议，模块文件和测试文件（test）。-Verilog FPGA code languages. Pc machine functions through a number of epp constantly write to the SRAM, and then pc send interrupt signals to interrupt the process of writing to read the data in the SRAM. rar package includes epp agreement, modules and test documents (test).
Platform: | Size: 43008 | Author: 苗苗 | Hits:

[VHDL-FPGA-Verilog] vhdl_rs232

Description: 使用FPGA透过RS232与PC的作沟通，
Platform: | Size: 3072 | Author: 苏山河 | Hits:

[VHDL-FPGA-Verilog] VHDL_2Ddwt_ALL

Description: 這是一個DWT的Verilog code,它的主要功用是PC與FPGA之間的DWT程序的溝通與傳輸-This is a DWT of the Verilog code, its main function is between the PC and FPGA communication DWT procedures and transmission
Platform: | Size: 1467392 | Author: chiahao | Hits:

[Picture Viewer] ejpgl-dev-0.251

Description: 嵌入式JPEG Encoder源码，适于PC和FPGA平台，方便移植，该版本为1.20的改进（1.20解压缩后可能无法使用）-JPEG Encoder embedded source, suitable for PC and FPGA platform for transplantation, the improvement of version 1.20 (1.20 after decompression may not be able to use)
Platform: | Size: 163840 | Author: 马振强 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 使用verilog作为CPU设计语言实现单数据通路五级流水线的CPU。具有32个通用寄存器、一个程序计数器PC、一个标志寄存器FLAG，一个堆栈寄存器STACK。存储器寻址粒度为字节。数据存储以32位字对准。采用32位定长指令格式，采用Load/Store结构，ALU指令采用三地址格式。支持有符号和无符号整数加、减、乘、除运算，并支持浮点数加、减、乘、除四种运算，支持与、或、异或、非4种逻辑运算，支持逻辑左移、逻辑右移、算术右移、循环右移4种移位运算，支持Load/Store操作，支持地址/立即数加载操作，支持无条件转移和为0转移、非0转移、无符号>转移、无符号<转移、有符号>转移、有符号<转移等条件转移。
Platform: | Size: 43008 | Author: haotianr | Hits:

[Windows Develop] USB-slavefifo

Description: 本组程序包括FPGA程序，固件程序和上位机程序，实现USB的数据传输功能，采用Slave Fifo模式，上位机程序利用Cypress公司提供的库函数进行开发-In this group include FPGA, firmware, procedures and PC procedures realize USB data transfer function, the Slave Fifo mode, host computer program using Cypress library functions provided by the company to develop
Platform: | Size: 5099520 | Author: 林颖 | Hits:

[VHDL-FPGA-Verilog] k21test

Description: 只需要FPGA两个通用管脚，就可以实现FPGA与PC机进行以太网通信！！如果你有ALTERA_DE1的开发板，可以直接下再看效果，用其他板子就要重新分配一下管脚，推荐使用电流输出。-Only two general-purpose FPGA pins, you can realize FPGA and Ethernet PC machine! ! If you have ALTERA_DE1 development board, you can look under the direct effect, with other board you will need to reconsider the distribution of pins, recommended the use of current output.
Platform: | Size: 880640 | Author: 245680 | Hits:

[Other Embeded program] Serial

Description: FPGA与PC串口通信的Verilog HDL 程序-FPGA and the PC serial communication procedures Verilog HDL
Platform: | Size: 2048 | Author: feng | Hits:

[USB develop] usb_VC

Description: usb数据采集-上位机程序vc完整工程（配合cypress的usb芯片使用）-usb data acquisition- complete PC vc program works (with the usb chip to use cypress)
Platform: | Size: 3603456 | Author: 郁闷 | Hits:

[USB develop] USB2.0FPGA_EXAMPLES

Description: FPGA与USB通信的测试代码，包括FPGA中的程序（Verilog编写）和PC机上的主控程序以及USB固件程序。-FPGA and the USB communication test code, including the FPGA in the procedure [Verilog prepared] and PC-control procedures, as well as the USB firmware.
Platform: | Size: 5515264 | Author: 李诚铭 | Hits:

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